三维TPC译码器的设计及FPGA实现

摘要

Turbo product code(TPC) is a kind of forward error correction code(FEC)with excellent performance. TPC has the advantages of low decoding complexity and short decoding delay,and can achieve near-optimum performance at low signal-to-noise ratio. The soft-in soft-out(SISO)iterative decoding method for three-dimensional(3D)TPC based on Chase algorithm is intro-duced. The hardware design scheme of 3-D TPC decoder is proposed and verified on FPGA platform. The simulation results show that the decoder has high error-correcting capability and meets the requirement of mobile communication on bit error rate.%Turbo乘积码（TPC）是一种性能优秀的纠错编码方法，它具有译码复杂度低、译码延时小等优点，且在低信噪比下可以获得近似最优的性能。介绍了基于Chase算法的三维TPC软输入软输出（SISO）迭代译码算法，提出了三维TPC译码器硬件设计方案并在FPGA芯片上进行了仿真和验证。测试结果表明，该译码器具有较高的纠错能力，满足移动通信误码率的要求。