Performance-driven Routing Tree Construction with Buffer Insertion and Wire Sizing

摘要

A new approach was proposed to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (RLC) delay model. This approach is based on the concept of sharing-buffer insertion and dynamic programming approach combined with a bottom-up rectilinear Steiner tree construction. The performances include the timing delay and the quality of signal waveform. The experimental results show that our proposed approach is scalable and obtains better performance than SP-tree and graph-RTBW approaches for the test signal nets.