一种面向片上互连的自适应通道双缓冲延迟模型

摘要

With the technology scaling down,relative to the gate delay, the global wire delay increases and hence a flit transmission between routers requires several cycles on Network-on-Chips(NoCs). Registers in pipelined channels cannot buffer flits when the congestion occurs in the credit-based flow control scheme. Therefore, an adaptive Channel Double Buffer (CDB), which can buffer flits, is proposed in the paper. With detailed design and analysis of the gate-level circuit, the delay model of the CDB is derived based on the theory of the logical effect. It is validated by Synopsys Prime Time in a TSMC 65 nm technology and found the difference within one t4. Experimental results show that the depth of the CDB is the same with the SPLS for a lmm semi-global interconnect wire in a 32nm technology.%随着集成电路工艺的等比例缩小,互连线延迟相对门延迟增加,导致报文在片上网络路由器之间的传输需要多个时钟周期.但是,在基于信用点流控策略中,物理链路中的寄存器在发生拥塞时不能够缓冲报文.因此,本文提出了一种自适应的通道双缓冲结构,能够在发生拥塞时缓冲报文.通过门级电路的设计和分析,根据逻辑努力方法建立了CDB的延迟模型.延迟模型的准确性利用Synopsys时序分析工具Prime Time在TSMC的65nm工艺库下被验证,两者相差不超过一个(τ)4.结果表明,在32nm工艺下,1mm长的半全局互连线通道双缓冲(CDB)和简单流水线(SPLS)所需要的级数相同.