基于FPGA的多加解密算法可重构的设计

摘要

基于FPGA实现加解密系统时, 采用多种算法处理数据可以适应不同的应用环境与功能需求, 但在同一片上实现多种算法会导致逻辑资源消耗增加、资源利用率低、系统灵活性差.针对以上问题, 以动态可重构技术为核心, 基于ZYNQ-7000系列FPGA设计动态可重构控制平台, 通过片上Cortex-A9ARM处理器控制重配置处理模块, 将存储于SD卡中的多种算法逻辑按功能需求配置到片上划定的逻辑分区中, 更新逻辑电路并完成算法重构.实验结果表明, 该设计能在片上其它功能正常工作的同时, 以15 759.51Bytes/ms的配置速度完成算法切换, 在保证系统稳定的前提下, 降低了片上的逻辑资源消耗, 提高了资源利用率与系统灵活性.%When implementing cryptographic system based on FPGA, using multiple encryption and decryption algorithms to process data matches the requirement of different applicant environment.But algorithms located in one place generates problems like increasing logical recourse, low resource utilization and deficient system flexibility.To solve those problems, a dynamic reconfigurable control platform on ZYNQ-7000 series chips of FPGA was designed.Reconfigurable processing unit was controlled using Cortex-A9 ARM processor and multiple algorithms stored in the SD cards were configured to designated logical partition according to functional requirements.Reconfiguration finished after logical circuit was updated.Results show that the proposed design can switch algorithms at the speed of 15 759.51 Bytes/ms, while other functional partitions still work normally.On the premise of ensuring system stability, the proposed design also reduces the on-chip logic resource consumption and improves the utilization rate of resources and system flexibility.