The logarithmic response CMOS image sensor provides a wide dynamic range (around 120dB), but its drawback in logarithmic image sensor design is the lack of simple fixed pattern noise (FPN) cancellation scheme. A Log-APS is employed for CMOS image sensor to achieve wider dynamic range than linear-APS. A novel FPN reduction technology is introduced to enable pixel FPN reduction in a logarithmic mode image sensor by additional transistor with double sampling circuit. This is a significantly high reduction in the FPN levels and it suggests that the double sampling technique with additional switch transistor is an efficient method for FPN reduction in the logarithmic mode of pixel output.%对数模式的CMOS图像传感器提供了大动态范围(大约120dB).在对数图像传感器设计中缺少简单的消除FPN的方法.采用对数模式的CMOS图像传感器获得了比线性APS大的动态范围.在对数模式传感器中采用了一种新的FPN抑制技术.即在对数像素中增加一个开关晶体管并结合双采样电路,该技术的实施使得对数像素的读出显著的降低了FPN水平.
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