用于时间延迟积分型图像传感器的流水采样列级运放共享累加器∗

摘要

提出了一种适用于TDI-CIS(时间延迟积分CMOS图像传感器)的模拟域流水采样列级运放共享累加器结构。提出的这种模拟累加器结构应用流水采样结构在不改变运放速率的前提下,将累加器的速率提升为传统累加器的2倍；采用积分电容列运放共享技术将n级TDI-CIS所需的运放个数减少至采用传统累加器所需个数的1/n。分析了流水采样累加器结构的原理以及输出噪声。使用标准0.18μm CMOS工艺进行了电路设计。仿真结果显示,提出的模拟累加器结构功耗为0.29 mW,采样率为2 Msample/s。结果表明流水采样列级运放共享累加器结构在保持低电路面积和功耗的同时,可将TDI-CIS最大可达到的行频增加一倍,更适于高速扫描的应用环境。%A novel pipelined sampling accumulator structure with opamp sharing technique is presented,which is fit for CMOS TDI( time-delay-integration) image sensor. The sampling speed of the analog accumulator can be doubled with only 1 opamp instead of n opamps for an n-stage accumulator. This structure decreases chip area and power dissipation and increases accumulating speed as well. This paper illustrates the topology of the proposed structure and analyzes the output noise. The proposed circuit is designed in a 0. 18 μm CMOS process. Simulation results show that the power dissipation of the proposed circuit is 0.29 mW under 3.3 V voltage supply,and the sampling rate of the accumulator is 2 Msample/s. It proves that the proposed accumulator structure is suitable to the applica-tion at high scanning speed.