一种用于数字下变频的高阶分布式FIR滤波器及FPGA实现

摘要

A 256-order distributed FIR filter for digital down conversion is described in this article. To analysis the impact on resource consumption and speed when implementation the circuit because of the structure of the HR filter, the structure of the circuit which is implemented on FPGA is determined. The algorithm is implemented on Cyclone Ⅲ EP3C40F484C6N ,after that the resource consumption and speed of FPGA is analyzed.%设计了一种用于数字下变频的256阶分布式FIR滤波器.通过分析分布式FIR滤器结构给实现电路所需资源和运算速度带来的影响,确定了适用于Cyclone Ⅲ系列FPGA的实现结构.在Cyclone Ⅲ系列EP3C40F484C6N芯片上实现该算法并分析了资源消耗与电路速度.