A Dataflow based Hardware Design Methodology for Digital Signal Processing Algorithms.

摘要

Current Digital Signal Processing (DSP) algorithms are increasingly complex and difficult to analyze and profile for hardware implementation at the early stages of a design. Although the high level design tools and system level languages accelerate the design process, they often prove to be inefficient and incapable of providing complexity analysis as a first step toward accomplishing the implementation of DSP algorithms. Additionally, DSP systems are designed by making gradual architectural choices in Hardware (HW) refinement steps. These decisions are based on performance quantification by high level DSP algorithm developers and HW implementation engineers. The main obstacle to this refinement is the provision of reasonably correct performance estimation to guide HW designers in design space exploration (DSE) at an early stage. Hardware designers are challenged to quantify their design decisions when they generate an efficient system. To tackle this challenge, we developed a dataflow based performance estimation methodology that will help HW designers quantify hardware performance. We use dataflow models to describe only the necessary hardware detail. The proposed quick estimation method will help to develop a methodology that facilitates the derivation of analytical models. This methodology proposes analytical dataflow models for quantifying the underlying algorithms' memory complexity, related timing considerations, and verification of the correctness of the DSP algorithm. We developed the necessary tools as needed in addition to existing dataflow tools, in order to efficiently and quickly estimate hardware performance. Additionally, we provide mathematical formulations and dataflow templates that HW designers may readily use for efficiently generating and optimizing their HW designs. The methodology has been validated by its application to the hardware design for DSP algorithms including the 2D Discrete Wavelet Transform. The experimental results present an advantage to HW designers for assessing design metrics compared to conventional methodologies. The dataflow based performance estimation achieves the efficient generation of qualitative and quantitative parameters for the assessment of HW candidates. The efficiency and efficacy of our method are confirmed by hardware implementation and analytical and simulation results. We believe that this can be extended easily for implementing two dimensional filtering algorithms in addition to Discrete Wavelet Transform (DWT).