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Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology.

机译:蓝宝石技术上使用CMOS硅的集成式DC-DC升压转换器。

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摘要

With the recent advancements in semiconductor manufacturing towards smaller, faster and more efficient microelectronic systems, the problems of increasing leakage current and reduced breakdown voltage in bulk-CMOS transistors have become substantial in the sub-100-nanometer era. The Peregrine UltraCMOS Silicon-on-Sapphire (SOS) technology that uses highly-insulating sapphire substrate as insulator was introduced to meet the continually growing need for higher performance RF products. The electrically isolated circuit elements in the UltraCMOS technology lead to increased switching speeds and lower power consumption due to reduced junction and parasitic capacitances. Furthermore, the growing need for high-speed switching applications such as boosting a lower voltage level to a higher one gives the UltraCMOS technology an upper hand over the bulk-CMOS process.;The limitation to using an UltraCMOS transistor is that its maximum drain to source voltage (VDS) swing is 2.5V. This thesis aims to address this limitation by studying and implementing various stacking techniques in high power switching applications where voltage switching of higher than 2.5V are required. Fully-integrated DC to DC boost converters with switching circuits based on dynamically self-biased stacked transistors are proposed. For high voltage and high power handling, the proposed stacking techniques equally distribute the overall output voltage to less than 2.5V across each stacked transistor in the switch (VDS of 2.5V).
机译:随着半导体制造朝着更小,更快和更高效的微电子系统发展的最新进展,在体积不足100纳米的时代,大体积CMOS晶体管中增加漏电流和降低击穿电压的问题变得十分重要。引入了Peregrine UltraCMOS蓝宝石硅(SOS)技术,该技术使用高度绝缘的蓝宝石衬底作为绝缘体,以满足对高性能RF产品不断增长的需求。由于减少了结和寄生电容,UltraCMOS技术中的电隔离电路元件可提高开关速度并降低功耗。此外,对高速开关应用的不断增长的需求,例如将较低的电压电平提升到较高的电压电平,使得UltraCMOS技术在体CMOS工艺上占据了上风。;使用UltraCMOS晶体管的局限在于其最大漏极消耗为电源电压(VDS)摆幅为2.5V。本文旨在通过研究和实现在需要高于2.5V电压切换的高功率开关应用中的各种堆叠技术来解决这一限制。提出了具有基于动态自偏置堆叠晶体管的开关电路的全集成式DC / DC升压转换器。对于高电压和高功率处理,建议的堆叠技术将整个输出电压平均分配到开关中每个堆叠晶体管上的2.5V以下(VDS为2.5V)。

著录项

  • 作者

    Mohammad, Imaduddin.;

  • 作者单位

    Purdue University.;

  • 授予单位 Purdue University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.E.C.E.
  • 年度 2014
  • 页码 83 p.
  • 总页数 83
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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