This work begins by laying out the motivation for investigations of photonic networks-on-chip, and reviews previous work at the device and system level. Then, within the logical framework for one photonic-network-on-chip design methodology in particular, this work describes the significant contributions of the author toward the design and experimental investigation of waveguides, modulators, and switches. Finally, based on device performance and system-level constraints, new designs are achieved which address the limitations of the former ones.;Experiments stressing large aggregated throughput are performed on both passive and active devices. For example, the transmission of more than 1 Tb/s of optical data through a 5-cm-long silicon photonic waveguide is successfully demonstrated; the experiment currently holds the record for the most optical bandwidth in a silicon photonic waveguide of any length. Additionally, active photonic switches are demonstrated with up to 250 Gb/s of bandwidth, although scalable to even larger values consistent with the waveguide capacity. High-speed switching is achieved in 1x2 and 2x2 switches based on carrier injection with switching times of only a few nanoseconds. These single-stage switch variations are then combined into a novel design to achieve a 4x4 non-blocking photonic router capable of multi-wavelength operation, ideal for the studied two-dimensional photonic network-on-chip topologies. The fabrication of this router, along with a complete experimental multi-wavelength routing verification, is described in the work. Indeed, wavelength parallelism is employed for bandwidth scaling in modulator experiments as well, showing four-channel operation of a modulator at 16 Gb/s (aggregate) using modulators which have been demonstrated elsewhere to achieve per-channel speeds of up to 18 Gb/s. Moreover, in each of these experiments performed on the waveguides, modulators, and switches, a high degree of signal integrity is affirmed through bit-error-rate measurements. These measurements quantify device power penalty and jitter, which are then used to identify the dominant sources of impairments. This knowledge facilitates refinements in future device designs, in addition to quantifying important system-level metrics which are required for optimal system implementations.;In addition to the contributions in the design and experimental characterization of the components for photonic networks-on-chip, this work also outlines recent experimental advances in parametrical optical processing systems that can be implemented with silicon waveguides. These processing systems leverage ultrafast time constants, allowing extremely high-speed switching for high-bandwidth time-division-multiplexed bit-stream manipulation, such as aggregation and de-aggregation of tributary streams, continuously tunable delays, and multicasting. The contributions of this work toward these aims are (1) to investigate the power penalty versus conversion bandwidth of simple wavelength converters at 10 Gb/s showing penalties less than 0.5 dB over a 20-nm range; (2) to demonstrate wavelength conversions at 40 Gb/s across nearly 50 nm and at 160 Gb/s across more than 20 nm, with a 40-Gb/s power penalty of 2.9 dB; (3) to show the first demonstration of wavelength multicasting on-chip, realizing up to 8-way multicasts with error-free (bit-error rates 10-12) operation. (Abstract shortened by UMI.)
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