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A CLASS OF ARITHMETIC BURST-ERROR-CORRECTING CODES FOR THE FIBONACCI COMPUTER.

机译:FIBONACCI计算机的一类算术突发错误校正代码。

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摘要

For computers whose main components are on a single chip, as microprocessors, the errors, instead of being randomly scattered, are more apt to be "localized" in the form of bursts in the chip. Burst-errors, also known as non-uniform errors, or errors to consecutive digits, are becoming an important and practical problem in these new computers and their resulting arithmetic coding theory. With technology moving toward making integrated circuit (I.C.) chips of groups of bits (the bytes) the building block units, burst-error-correcting codes are useful indeed.;The Fibonacci numbers are proposed as a new number base system for computers, which could lead to more error-free operations. The motivation to use these numbers comes from a property of considerable importance: the existence of a non-adjacent-form Fibonacci representation of integers.;This study is divided into four major parts: (1) section one formulates the Fibonacci number system. (2) section two shows the implementation of the Fibonacci Computer's Arithmetic Unit using existing binary logic. (3) section three studies the two basic Fibonacci arithmetic codes: the Fibonacci AN codes and the Fibonacci biresidue codes. (4) section four gives the theory of the Fibonacci burst-error-correcting AN codes.;It is the intention of this study to demonstrate that the Fibonacci computer's architecture produces more superior arithmetic burst-error-correcting codes than their binary system's counterparts. This "burst-error-correcting" property, not seen in the binary system, makes Fibonacci computer theoretically interesting as well as practically important.;In order to produce better burst-error-correcting codes, it is felt that not only the present day hardware needs to be improved but also a better number base is needed to be developed in which the computer does its calculation, as well as a superior coding theory.
机译:对于主要组件在单个芯片上的计算机,作为微处理器,错误而不是随机分散,更倾向于以突发形式在芯片中“定位”。突发错误,也称为非均匀错误或连续数字错误,正在成为这些新型计算机及其由此产生的算术编码理论中的一个重要而实际的问题。随着技术朝着以比特(字节)组的集成电路(IC)芯片为构建单元的发展,突发错误校正码的确是有用的。斐波那契数被提出作为计算机的一种新的数基系统,可能会导致更多的无错误操作。使用这些数字的动机来自一个非常重要的性质:存在整数的非相邻形式的斐波那契表示形式。本研究分为四个主要部分:(1)第一部分阐述了斐波那契数字系统。 (2)第二部分显示了使用现有二进制逻辑实现Fibonacci计算机算术单元的方法。 (3)第三节研究了两个基本的斐波那契算术代码:斐波那契AN代码和斐波那契双残差代码。 (4)第四部分给出了Fibonacci突发错误校正AN代码的理论。本研究的目的是证明Fibonacci计算机的体系结构比二进制系统的同类产品产生更出色的算术突发错误校正代码。这种“突发错误校正”特性在二进制系统中不可见,这使斐波那契计算机在理论上很有趣,而且在实践中很重要。为了产生更好的突发错误校正码,人们感到不仅是今天硬件需要改进,但还需要开发更好的数字基础,计算机可以在其中进行计算,并需要使用高级的编码理论。

著录项

  • 作者

    HOANG, VIET-DUNG.;

  • 作者单位

    University of Maryland, College Park.;

  • 授予单位 University of Maryland, College Park.;
  • 学科 Engineering Electronics and Electrical.;Computer Science.
  • 学位 Ph.D.
  • 年度 1979
  • 页码 102 p.
  • 总页数 102
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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