On multiprocessor dataflow parallel pipelined processors in image processing.

摘要

Image processing involves manipulations of huge amounts of data which is currently handled by von Neumann architecture machines. These operations have parallelism at various levels which makes the sequential natured von Neumann architecture undesirable. In this paper an alternative approach via the non von Neumann architecture based state of the art devices is discussed. The paper includes the implementation of an inexpensive multiprocessor pipelined dataflow processor. Problems associated with the implementation are discussed and suggestions for improvement are made. The discussion will be approached with a hardware point of view with reference to the merits and relevance of the architecture as applied to image processing.