Issues in the design of pipelined VLSI circuits for DSP applications.

摘要

High speed implementation of Digital Signal Processing circuits is essential for communication, control and multimedia applications. Pipelining is a commonly used approach to improve the speed performance of a circuit. In this research, two different schemes of pipelining are examined. The wave-pipelined approach is intended for high throughput custom designs. The bit-leveled pipelined approach for FPGA implementation is intended for medium to high speed applications with reconfigurable needs.; The wave pipelined approach is an attractive alternative to conventional pipelining in achieving high speed, low power and low cost solutions. In conventional pipelining, latching elements and clock networks results in large area and high power consumption. Wave pipelining does not require such latching elements or global clock networks. High throughput pipelining is achieved using specific circuit and layout design methods. In this research, issues involved in the wave pipelined design process are examined in detail and solution methods developed. An overall approach to the wave pipelined DSP circuit design problem is presented, including the design of suitable logic gate family, analytical tools to improve the design process, optimum circuit structures for arithmetic and DSP elements and high speed on-chip testing circuits. Both the custom hardwired and programmable processor Implementations of the DSP algorithms are examined. Simulation and test results of the designs and algorithms are presented. Throughputs of 300-400MHz is achieved using 1.2-micron technology. The speed and power performance results validate the use of wave pipelining for high performance DSP circuit implementation.; For applications with moderately high throughput and more emphasis on design cost and flexibility, Field Programmable Gate Array (FPGA) devices offer an attractive solution. In this research, a bit-level pipelined approach to implement DSP circuits is developed to achieve high throughput with optimum use of the device resources. Efficient layout and routing schemes for typical DSP circuits are developed. The simulation results with existing FPGA devices show the effectiveness of this approach. Throughput of 100MHz is reached with Xilinx XC4000 devices with 5-ns block delay. An analysis of the resource requirements for a DSP FPGA is also presented as a groundwork for developing such devices.