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ASIC implementation of the symmetric fuzzy processor and its application to adaptive systems.

机译:对称模糊处理器的ASIC实现及其在自适应系统中的应用。

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This dissertation presents a VLSI design of a symmetric fuzzy processor. The design features fuzzification, defuzzification and inference operations while allowing the implementation of a knowledge base via rules. By combining the inherent advantages of symmetric triangular membership functions and fuzzy singleton sets, a novel structure for the fuzzification model is obtained. The structure accelerates the evaluation of the antecedent degree which is evaluated by a simple mathematical relation which calculates the resulting value using the end-points of matched fuzzy member functions. This feature enables the processor to avoid the requirement of storing all the sample values of the fuzzy membership function in memory as is the case with other approaches. In addition, the resulting design structure simplifies computations associated with centroid defuzzication in that certain simplifying assumptions eliminate the need for a divider circuit. By using a very high speed integrated circuit hardware description language (VHDL) compiler and by making use of a simulator provided through the Mentor Graphics EDA design tool, optimization of the VLSI design has been obtained. Results show that the resulting fuzzy processor can be implemented on a single 1.2{dollar}mu{dollar}m CMOS VLSI chip with 16.7 mm{dollar}sp2{dollar} die size and a total of 36,080 transistors. Moreover, simulation indicates that numerical computations including centroid defuzzification can be accomplished in 0.55 {dollar}mu{dollar}s. within an accuracy of 96%, thus making it suitable for a wide range of real-time applications. Up to 49 consequent knowledge rules based for seven fuzzy membership functions associated with the chip's two input variables can be downloaded into a 64-byte static RAM allowing designers to create a fuzzy processing system without the need for additional on-board memory. Finally, as an example of the application of the proposed fuzzy processor model, results are presented from a study to simulate a second order linear control system and a non-linear structure for adaptive channel equalization of a bipolar signal passed through a dispersive channel in the presence of additive noise. It is shown that difficulties commonly associated with channel non-linearity and additive noise correlation can be overcome by the use of an equalizer employing the developed fuzzy structure.
机译:本文提出了一种对称模糊处理器的VLSI设计。该设计具有模糊化,反模糊化和推理操作的功能,同时允许通过规则实现知识库。通过结合对称三角隶属函数和模糊单例集的固有优势,获得了一种新型的模糊化模型结构。该结构加快了对先验程度的评估,后者通过简单的数学关系进行评估,该数学关系使用匹配的模糊成员函数的端点计算结果值。此功能使处理器可以避免像其他方法一样将模糊隶属度函数的所有样本值存储在内存中的需求。此外,最终的设计结构简化了与质心去模糊相关的计算,因为某些简化的假设消除了对分频器电路的需求。通过使用超高速集成电路硬件描述语言(VHDL)编译器,并利用通过Mentor Graphics EDA设计工具提供的仿真器,可以实现VLSI设计的优化。结果表明,所得模糊处理器可在单个1.2微米CMOS VLSI芯片上实现,芯片尺寸为16.7毫米sp2,总共有36,080个晶体管。此外,仿真表明,包括质心去模糊化在内的数值计算可以在0.55 {μm}μμs之间完成。在96%的精度范围内,因此使其适用于各种实时应用。可以将基于与芯片的两个输入变量关联的七个模糊隶属函数的多达49个相应的知识规则下载到64字节的静态RAM中,从而允许设计人员创建模糊处理系统,而无需额外的板上存储器。最后,以所提出的模糊处理器模型的应用为例,给出了一项研究结果,用于模拟二阶线性控制系统和非线性结构,该非线性结构用于自适应双通道信号通过分散通道时的自适应通道均衡。存在附加噪声。结果表明,通常可以通过采用采用模糊结构的均衡器来克服通常与信道非线性和附加噪声相关性相关的困难。

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