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An integrated process modeling methodology and module for sequential multilayered high-density substrate fabrication for microelectronic packages.

机译:用于微电子封装的顺序多层高密度基板制造的集成工艺建模方法学和模块。

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摘要

The growing complexity of electronic circuits and the miniaturization of electronic components has generated significant interest in high-density-wiring (HDW) substrates with finer line widths and spaces and embedded passives. Typically, the HDW substrate fabrication process involves the sequential deposition of alternate layers of copper metallization and polymer dielectric on a base substrate, with photolithographic definition of the interconnect vias. Warpage and stresses arise in such multilayered structures during the sequential fabrication due to the thermal gradients and the mismatch in thermomechanical properties between the different materials. The thermally-induced stresses could result in various failure mechanisms such as delamination or debonding of the layers, interconnect via cracking, and film cracking. The thermally-induced warpage, on the other hand, could lead to misregistration and reduced tolerance and accuracy of the fine interconnect features, as well as misalignment problems during package assembly. Therefore, due to the presence of several new material systems and processing conditions, the traditional build-and-test approach is not cost-effective for designing such multilayered substrates, and an innovative virtual prototyping methodology is required.; In this research, an integrated process modeling methodology and module has been developed for simulating the large-area fabrication of a HDW substrate. This consists of a fully-coupled cure kinetics-heat transfer-stress finite element analysis approach, where the deposition and curing of the interlayer polymer dielectric on a base substrate has been simulated by activating the respective material elements at the gel point. An extensive investigation of the curing behavior and characterization of the thermomechanical material properties has been done for the selected thin film photo-dielectric dry film (PDDF) material, Vialux 81™. Phenomenological models have been developed for the cure kinetics, the cure-induced shrinkage and the cure-dependent viscoelastic stress relaxation modulus. These models have been incorporated into the integrated process modeling module through user-defined subroutines for the exothermic heat liberated during curing, and the cure-dependent, isotropic, linear viscoelastic behavior, inclusive of cure shrinkage and thermal expansion/contraction effects. Experimental validation of the time and temperature-dependent evolution of warpage and stress during the polymer curing process has been done to verify the results from the process models. In addition, a cure process optimization strategy has been devised, and the fabrication of microvias and fine features has been demonstrated.
机译:电子电路的日益复杂和电子部件的小型化引起了人们对具有更细的线宽和间距以及嵌入式无源元件的高密度布线(HDW)基板的极大兴趣。通常,HDW基板制造工艺涉及在基础基板上依次沉积铜金属化层和聚合物电介质的交替层,并用光刻技术定义互连通孔。由于不同材料之间的热梯度和热机械性能的不匹配,在连续制造期间在这种多层结构中会出现翘曲和应力。热引起的应力可能会导致各种失效机制,例如层的分层或剥离,通过裂纹相互连接以及薄膜裂纹。另一方面,热引起的翘曲可能导致配准错误,并降低精细互连部件的公差和精度,以及封装组装过程中的对准问题。因此,由于存在几种新的材料系统和加工条件,传统的构建和测试方法对于设计这种多层基板并不具有成本效益,因此需要一种创新的虚拟原型方法。在这项研究中,已经开发了一种集成的工艺建模方法和模块,用于模拟HDW基板的大面积制造。这由完全耦合的固化动力学-传热-应力有限元分析方法组成,其中通过激活胶凝点上的各个材料元素模拟了层间聚合物电介质在基础基材上的沉积和固化。对于选定的薄膜光介电干膜(PDDF)材料Vialux 81™,已经完成了对固化行为和热机械材料性能表征的广泛研究。已经开发了用于固化动力学,固化引起的收缩和依赖于固化的粘弹性应力松弛模量的现象学模型。这些模型已通过用户定义的子例程并用于集成过程建模模块,这些子例程用于固化过程中释放的放热以及与固化相关的各向同性线性粘弹性行为,包括固化收缩和热膨胀/收缩效应。已经进行了聚合物固化过程中翘曲和应力随时间和温度变化的实验验证,以验证过程模型的结果。此外,还设计了一种固化工艺优化策略,并演示了微孔和精细特征的制造。

著录项

  • 作者

    Dunne, Rajiv Carl.;

  • 作者单位

    Georgia Institute of Technology.;

  • 授予单位 Georgia Institute of Technology.;
  • 学科 Engineering Mechanical.
  • 学位 Ph.D.
  • 年度 2000
  • 页码 215 p.
  • 总页数 215
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 机械、仪表工业;
  • 关键词

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