Integrated logic and physical design for deep submicron VLSI optimization.

摘要

Circuit speed is one of the most important criteria for today's circuit designers. Since the minimum feature size of VLSI circuits reached the Deep Submicron (DSM) range, interconnects have become the dominant factor in determining the circuit speed. However, conventional Computer Aided Design tools and flows, which separate the front-end logic design from the back-end physical design, cannot achieve the maximum performance capability provided by the silicon fabrication process. Consequently, it has become necessary to develop and introduce new design automation techniques and design flows to fill the gap between the design tool capabilities and the silicon fabrication process potential. In recent years, integrated logic and physical co-design flows, which globally interleave and locally integrate front-end logic design and back-end physical design, have been widely accepted by design teams as the next generation in design methodology. In this new flow, front-end tools receive accurate interconnect parasitic data and power/delay/signal integrity estimates from the back-end tools, and pass detailed logical information and power/timing constraints to the back-end tools.; In this dissertation, a number of algorithms that perform integrated logic and physical optimizations at different stages in a logic and physical co-design flow are presented. The goal is to increase the operating speed of DSM circuits and achieve fast timing closure. First, a post-synthesis and pre-layout, simultaneous gate sizing and fanout optimization algorithm is presented. A continuous-variable delay model reflecting delay changes due to gate sizing and/or buffer tree insertion is provided. Based on this model, path delays of the circuit are optimized by a mathematical programming method. Next, a post-layout concurrent gate sizing and placement algorithm is presented. The technique consists of formulating the sizing and placement problem as a generalized geometric program. To control the problem size, an iterative optimization process is performed where the critical paths are identified and optimized in an iterative manner. Finally, a dynamic programming-based algorithm that constructs buffered routing trees under buffer placement blockages is presented. The proposed algorithm performs buffer insertion and sizing along with routing tree generation in one step.