Advanced VHDL fault models for analysis of fault secure CMOS ICs.

摘要

This thesis presents two new and innovative fault models that are appropriate for analysis of fault secure CMOS ICs. Popular existing fault models sacrifice accuracy and realism to achieve simplicity and efficient simulation speed. However, due to the potentially serious consequences that can result from failure of fault secure circuits, it is unacceptable to conduct verification using inaccurate models.; Two new fault models, implemented using a structural VHDL approach, are proposed for cell-level transistor defects and interconnect bridge defects. These models are unique in that they are derived from extensive analog simulation and support full-timing simulation, with due attention to the load characteristics surrounding the defect site. The new cell-level fault model is the first of its kind to incorporate VITAL compliance, which provides an industry standard level of accuracy in conjunction with efficient simulation performance. The new bridge fault model is the only known approach that uses a neural network to compute node voltages and signal propagation delay times. Accuracy tests show that it is capable of computing bridged node voltages with an average error near 0.006 volts and propagation delay times with an average error near 14 ps.; Several fault secure testbench circuits, based on the popular Data Encryption Standard (DES) algorithm, are used to demonstrate the new fault models. Exhaustive cell-level fault simulation and extensive bridge simulation provide an indication of the relative fault security of each circuit. This enables an objective comparison between different design alternatives with respect to fault security attributes along with area, power, and delay considerations.