CMOS image sensors offer lower cost and the potential for higher levels of system integration than do charge coupled device (CCD) imager sensors. To take full advantage of this potential for system integration, it will be necessary to migrate imager designs to more advanced CMOS processes, as technology scales. This in turn will require the design of imagers capable of operating with greatly reduced power supply voltages compared to those now commonly in use. Reduction in power supply voltage is known to degrade the dynamic range of conventional imagers.; A CMOS imager designed and fabricated in a 0.18 μm digital CMOS technology operating from a 1.2V power supply is presented in this thesis. The imager uses column parallel, second-order delta-sigma analog-to-digital converters, along with a digital signal processing technique to achieve high dynamic range for this low supply voltage. In experimental tests the imager was shown capable of measuring input light levels ranging over 5 orders of magnitude.
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