Parallel discrete event simulation and its application on logic simulation.

摘要

The purpose of this PhD dissertation is to investigate new and efficient paradigms for parallel discrete event simulation on massively parallel processors and its application on parallel logic simulation. We first develop performance prediction models of parallel simulation. Using the performance models, we will identify critical factors for improving the performance of simulation. Among them, we will consider load balancing, communication cost, computational granularity, activity rate, and rollback rate.; Based on the importance of these factors, we will investigate new and improved approaches of parallel simulation. The first approach we consider is an aggressive synchronous algorithm to reduce the simulation cycles. This method reduces the communication cost and speedup of the simulation significantly. Next, a look-ahead technique will be investigated to reduce the state savings and the event queue size in Time Warp. The technique reduces the number of state savings by skipping state savings that is not necessary. Event queue and state queue sizes can be reduced by discarding the unnecessary events and states immediately. Finally, we will develop a unifying simulation framework that exploits the advantages of synchronous and conservative simulation techniques while keeping the optimism. The performance of this approach is always better than Time Warp and comparable to the best-case performance of synchronous and conservative simulation.