Improving icache hit rates in ILP architectures.

摘要

This dissertation investigates the relationships between icache performance and several modern architectural and compilation techniques. Specifically, it looks at the effects of icache associativity on obtained IPC (Instructions Per Cycle) for three areas. The first of these is a standard set of benchmarks running in a single context superscalar environment. The second area is a superscalar context switching environment, and the third is the application of loop unrolling to increase exploitable loop ILP. In all three of these areas, both hardware ILP and icache associativity are varied to determine which combinations are useful and which interact poorly.; Prior to this work, none of these interactions had been adequately explored. Many papers choose to either ignore their effects, or to rely on outdated research. The purpose of this research is to provide contemporary data and analysis about these interactions.; This dissertation finds that limited associativity can, in general, increase the average IPC for a benchmark. With the exception of a multi-context environment, however, full associativity provides little or no benefit. For a multi-context environment, full associativity can remove all the icache misses due to thrashing. This work also finds that associativity interacts poorly with loop unrolling, as it leads to an increase in icache miss rate. This increase is large enough to counter the performance increase from the unrolling, leading to a net performance loss.