Post-layout is an important stage in the modern VLSI design. In this stage, the extraction and verification tools can get the most accurate results with the complete layout information. The design problems can be detected precisely for further improvements or optimizations. But the problem is that the optimization is very hard to perform in post-layout. Every design modification is under tight geometry constraints. Usually the designer either changes layout manually, or goes back to previous design stages in order to have the preferred results. How to modify the layout becomes a bottleneck in the post-layout optimization. In this research we propose a new method to solve this problem, which is based on the topological representation of the layout. At first we developed a new topological layout encoding model, Triangulation Encoding Graph. Compared with other encoding models, the Triangulation Encoding Graph achieves both compact data size and efficient layout operations. Based on this encoding model, we further developed a set of topological layout operations, including topological design rule check, topological layout update and design rule violation solver. A post-layout optimization system, TEG, has been developed with these layout operations. Experimental results show that our topological method is efficient and effective in processing industry VLSI designs.
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