A 20-GHz bipolar varactor-tuned VCO using switched capacitors to add tuning range.

摘要

The increasing demand for telecommunication bandwidth has driven data rates increasingly higher. To meet the eventual demand for more bandwidth next generation systems are slated to run at 40GB/s. Although, it may be possible to implement 40GB/s data rates in advanced materials such as GaAs or InP eventually the clock and data recovery (CDR) circuits for these systems will have to be designed in a silicon (Si) technology.; In this thesis, the affects of various noise sources on the phase-locked loop (PLL) of a CDR circuit are simulated and discussed. Drawing from the simulation results, suggestions for the selection of CDR PLL loop parameters are given. As well, a dual-rate (10/20GHz) CDR PLL is discussed.; The most difficult block to design in a CDR PLL is the oscillator. If a VCO is used, it must be designed so that it has a large enough tuning range (+/-10%) to make up for variations in manufacturing. To accomplish this, a 20-GHz voltage-controlled oscillator (VCO) with on-chip inductors is presented. Wide-band tuning is accomplished in this VCO using a combination of switched capacitors and varactor diodes. Design guidelines for the oscillator and guidelines for switched-capacitor circuit design are given.; Finally, the VCO in simulation had a worst case phase noise performance of -73.5dBc/Hz at a 100kHz offset from a 20GHz carrier. Measurement results were not able to corroborate the simulation results. The reasons for the measurement failure is analysed.