Conception d'un plot reconfigurable pour un reseau de distribution de puissance a l'echelle de la tranche en technologie CMOS.

摘要

Nowadays, electronic systems integrate increasingly complex technical and economical constraints. The demand for less power hungry and smaller circuits, while offering improved performances, is crucial as much as time to market. There have been previous efforts to overcome the design, prototyping and debugging costs of high-end electronics systems, but none has succeeded in all the areas needed to revolutionize system design, prototyping and debugging.;A programmable pad is presented, pad that will be photo-repeated by a number of up to 1.3 M times and can be configured in different output configurations. The first one is a power distribution network consisting of a very dense array of voltage regulators able to supply standard levels of 1.0, 1.5, 1.8, 2.0, 2.5 and 3.3 V. The propagation of digital signals from an interconnection network must be asserted by the same output of the proposed pad. It can be programmed as a digital output of the same standard voltage levels or as an input that complies with any signal varying from 1.0 to 3.3 V. Finally, the same access point can also be configured as a ground or floating node and possesses a contact detection circuitry to detect any shortcircuits with its neighbour.;The first contribution of this master's thesis consists of integrating multiple functions such as programmable voltage regulation and digital input/output into a common output. The second major contribution is the reduction of the needed silicon area and quiescent current by many orders of magnitude while offering better or equal performances regarding the hierarchical voltage regulator.;A testchip has been fabricated in 180 nm CMOS from the Tower Jazz foundry located in Israel, and tested in our lab. The embedded regulators were programmed and the targeted voltage of 1.0, 1.5, 1.8, 2.0, 2.5 and 3.0 V were obtained with a maximum DC current as high as 110 mA. The obtained dynamic impedance is around 1 O resulting in a voltage variation of less than 10 % for a 100 mA load using no decoupling capacitance. The input-output function was validated at 10 MHz with a test bench designed for low-frequencies. The contact detection was also successfully validated. The area of silicon used is 0.00847 mm2 with a quiescent current around 5.85 muA.;Our main objective, in this master thesis, is the implementation of integrated circuits dedicated to a platform for rapid prototyping of digital systems. The main purpose of this platform is to offer systems designers a tool to help designing, testing and debugging complex electronic systems in a shorter time frame. Where months where previously needed, days are now required.