State-of-the-art VLSI circuit design requires extensive and expensive circuit simulation during circuit design and verification. Thus, the demand of increasing circuit simulation speeds has progressively strengthened. In this dissertation I review the existing algorithms and technologies in current simulators, and then present a fast analog circuit simulation algorithm, fundamental circuit based SPICE simulation, for circuit design and verification. For circuits being repeatedly modified during design and verification phases, the algorithm reuses previously simulation results on modified circuits to reduce operational redundancies. The algorithm is implemented with a standard SPICE simulator and applied to linear circuit applications directly. Following that, the nonlinear device delta models are developed to facilitate approaches to nonlinear circuit applications. The experiments show the algorithm increases circuit simulation speed up to ten (10) times over conventional simulations without losing accuracy.
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