Low power design methodologies in analog blocks of CMOS image sensors.

摘要

Complementary metal-oxide-semiconductor (CMOS) active pixel image sensors (APS) have been widely used in many portable devices, such as digital cameras, mobile phones, laptop computers, and bio-sensors. Power consumption is a critical issue in portable applications due to the limitation of the battery lifetime. This thesis describes research on low-power design for CMOS image sensors, in which low-power design techniques at the circuit level are addressed. Power reduction in the analog blocks of these mixed-signal devices is much more difficult than the digital blocks, because simple power supply scaling can significantly affect their performance. Two major issues related to low-power design in the analog blocks of CMOS image sensors using modern sub-micron processing technologies are studied in this research: maintaining acceptable dynamic range at lowered power supplies, and power minimization for a required performance.;Low-power design is facilitated by using automatic analog synthesis power optimization, with which a power optimal design can be achieved efficiently for a required performance. Here, a new sub-space-based posynomial modeling method is shown to increase the MOS transistor modeling performance for sub-micron technologies. Geometric programming (GP) based power optimization using sub-space-based posynomial models has been demonstrated to be an efficient and reliable low-power design technique in analog circuits. New techniques for solving speed-driven problems using GP in basic analog building blocks of CMOS image sensors were also shown. The sub-space modeling based GP synthesis was successfully applied to three major analog blocks (in-pixel source follower, correlated double sampling circuit, and analog-to-digital converter) of CMOS image sensors to achieve power-optimal designs. Synthesized circuits for these three blocks were verified with HSPICE simulations, and op-amps for a correlated double sampling circuit were verified experimentally with a fabricated chip. Both simulation and test results show that sub-space modeling based GP synthesis is an efficient and reliable power reduction technology in sub-micron technologies.;Dynamic range enhancement is a practical technique to overcome the output swing reduction caused by lowered power supplies. As an example of an application requiring a high dynamic range, a CMOS image sensor using a new predictive integration technique was designed for laser rangefinding. This design achieved ∼100-dB dynamic range when the power supply was kept as low as 1.8 V.