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Design of a 100+ meter 12Gb/s/Lane Copper Cable Link Based on Clock-Forwarding.

机译:基于时钟转发的100米以上12Gb / s /车道铜缆链路设计。

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摘要

As data centers are expected to manage the increasing demands in bandwidth, processing power and storage requirements, connectivity issues between blades/racks present a whole new set of challenges in maintaining a stable infrastructure. While data centers may grow to occupy thousands of square feet, current passive copper interconnects pose a real limitation with a run length of 10 meters at 10Gbps per wire pair. Optical fiber can extend the interconnection length from 10 meters to 100 meters, but the large power requirements and expensive opto-electric modules prove to be too uneconomical for practical application. As a compromise, through the use of the Infiniband standard, a 12Gbps cable link can be achieved that would extend the range of copper interconnects beyond the 100 meter threshold.;The proposed link leverages synchronous clock forwarding on one available data channel that improves jitter tracking, while greatly simplifying the design of the receiver and timing recovery circuits. Only a phase de-skewing is required at the receive side to retrieve the clock-data relationship. In the cable link architecture, the 12 Gbps data is repeated in 8 meter sections with clocking forwarding on a dedicated channel. Then the forwarded clock is dropped off every data repeating stage in order to be multiplied to half the data rate and be used to strobe the incoming data. The longer the quality of clock forwarding is maintained, the cleaner the data strobed at each repeater and the longer the cable can be extended. At each repeater, the clock resets the jitter accumulated from the previous repeater, allowing for data transmission with as much jitter as in the strobing clock.;Determining a fine balance in forward clock frequency is crucial in defining jitter performance of the cable link. Frequency beyond the cable bandwidth results in large attenuation of clock amplitude creating more noise and jitter accumulation along clock repeater. On the other hand, frequency well below the cable bandwidth will increase jitter accumulation time and will degrade jitter performance inside the clock multiplier. The trade-off between low frequency clock jitter accumulation in the Clock Multiplication Unit (CMU) and the high frequency jitter accumulation along the clock repeaters is one of the defining aspects of optimizing the active copper link.;To further reduce the clock jitter accumulation across repeaters, phase interpolation between the input clock and the divided output of the CMU is used to generate the forward clock for the next repeater stage. The addition of the phase interpolator has negligible power/area cost, dramatically reduces jitter accumulation, and adds another degree of flexibility in choosing the forwarded clock to reduce the total accumulated jitter. With the proper choice of forward clock frequency, application of the FIR filtering technique and a high performance CMU, a total run length of 115 meters is achieved at 12Gbps data rate.
机译:随着数据中心有望满足对带宽,处理能力和存储要求不断增长的需求,刀片式服务器/机架之间的连接性问题为维护稳定的基础架构提出了全新的挑战。尽管数据中心可能会扩大到数千平方英尺,但目前的无源铜互连却构成了真正的限制,其运行长度为10米,每对线对的速率为10Gbps。光纤可以将互连长度从10米延长到100米,但是大功率需求和昂贵的光电模块被证明对于实际应用来说太不经济了。作为一种折衷,通过使用Infiniband标准,可以实现12Gbps电缆链路,从而将铜互连的范围扩展到超过100米的阈值。建议的链路在一个可用数据通道上利用同步时钟转发,从而改善了抖动跟踪,同时大大简化了接收机和定时恢复电路的设计。在接收端只需要进行相位偏移即可检索时钟数据关系。在电缆链路体系结构中,在8米长的部分中重复12 Gbps数据,并在专用通道上进行时钟转发。然后,将转发的时钟从每个数据重复级中删除,以便倍增至数据速率的一半,并用于选通输入数据。保持时钟转发质量的时间越长,在每个转发器上选通的数据越干净,电缆的延伸时间就越长。在每个中继器处,时钟都会重置前一个中继器所累积的抖动,从而使数据传输时的抖动与选通时钟中的抖动相同。确定正向时钟频率的良好平衡对于定义电缆链路的抖动性能至关重要。超出电缆带宽的频率会导致时钟幅度大大衰减,从而在时钟转发器上产生更多的噪声和抖动累积。另一方面,低于电缆带宽的频率将增加抖动累积时间,并使时钟倍频器内部的抖动性能下降。时钟乘法单元(CMU)中的低频时钟抖动累积与沿时钟转发器的高频抖动累积之间的权衡是优化有源铜缆链路的决定性方面之一。在中继器中,输入时钟和CMU的分频输出之间的相位插值用于生成下一个中继器级的正向时钟。相位内插器的添加具有可忽略的功率/面积成本,大大减少了抖动累积,并且在选择转发时钟以减少总累积抖动方面增加了另一种灵活性。通过正确选择正向时钟频率,应用FIR滤波技术和高性能CMU,在12Gbps数据速率下可实现115米的总运行长度。

著录项

  • 作者

    Mohammed Ali, Tamer A.;

  • 作者单位

    University of California, Los Angeles.;

  • 授予单位 University of California, Los Angeles.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2012
  • 页码 89 p.
  • 总页数 89
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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