This dissertation presents a high performance hardware implementation of the IRS algorithm system using a modern digital signal processing (DSP) board. Using the ('C6711 DSK) board and its software, Code Composer Studio (CCS), we reviewed the IRS algorithm system and C code to see what should be modified and added in order to achieve the high performance implementation of the IRS algorithm system experimentally.; After we verified that the IRS algorithm system was successfully working on the board, we gradually increased the symbol length until we reached 16,384 samples. Moreover, we addressed the implementation of each part of the system: the transmitter, receiver, and channel. In addition, we applied this IRS algorithm system to different multipath channels. Thus, the hardware implementation performance of this algorithm in the presence of noise (AWGN) and multipath channels was studied based on the bit error rate (BER) curves. We also evaluated the execution time, memory usage, and real time performance.; Finally, we find the theoretical and experimental results very close to each other that they differ only by 0.5 dB. Therefore, we conclude that the results are reliable and the implementation of the IRS system on the board performs well in such environments.
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