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Characterization of High-Resistivity Silicon Bulk and Silicon-on-Insulator Wafers.

机译:高电阻率硅块体和绝缘体上硅片的表征。

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摘要

High-Resistivity Silicon (HRS) substrates are important for low-loss, high-performance microwave and millimeter wave devices in high-frequency telecommunication systems. The highest resistivity of up to ∼10,000 ohm.cm is Float Zone (FZ) grown Si which is produced in small quantities and moderate wafer diameter. The more common Czochralski (CZ) Si can achieve resistivities of around 1000 ohm.cm, but the wafers contain oxygen that can lead to thermal donor formation with donor concentration significantly higher (∼1015 cm -3) than the dopant concentration (∼1012--10 13 cm-3) of such high-resistivity Si leading to resistivity changes and possible type conversion of high-resistivity p-type silicon. In this research capacitance-voltage (C-V) characterization is employed to study the donor formation and type conversion of p-type High-resistivity Silicon-On-Insulator (HRSOI) wafers and the challenges involved in C-V characterization of HRSOI wafers using a Schottky contact are highlighted. The maximum capacitance of bulk or Silicon-On-Insulator (SOI) wafers is governed by the gate/contact area. During C-V characterization of high-resistivity SOI wafers with aluminum contacts directly on the Si film (Schottky contact); it was observed that the maximum capacitance is much higher than that due to the contact area, suggesting bias spreading due to the distributed transmission line of the film resistance and the buried oxide capacitance. In addition, an "S"-shape C-V plot was observed in the accumulation region. The effects of various factors, such as: frequency, contact and substrate sizes, gate oxide, SOI film thickness, film and substrate doping, carrier lifetime, contact work-function, temperature, light, annealing temperature and radiation on the C-V characteristics of HRSOI wafers are studied.;HRSOI wafers have the best crosstalk prevention capability compared to other types of wafers, which plays a major role in system-on-chip configuration to prevent coupling between high frequency digital and sensitive analog circuits. Substrate crosstalk in HRSOI and various factors affecting the crosstalk, such as: substrate resistivity, separation between devices, buried oxide (BOX) thickness, radiation, temperature, annealing, light, and device types are discussed. Also various ways to minimize substrate crosstalk are studied and a new characterization method is proposed.;Owing to their very low doping concentrations and the presence of oxygen in CZ wafers, HRS wafers pose a challenge in resistivity measurement using conventional techniques such as four-point probe and Hall measurement methods. In this research the challenges in accurate resistivity measurement using four-point probe, Hall method, and C-V profile are highlighted and a novel approach to extract resistivity of HRS wafers based on Impedance Spectroscopy measurements using polymer dielectrics such as Polystyrene and Poly Methyl Methacrylate (PMMA) is proposed.
机译:高阻硅(HRS)基板对于高频电信系统中的低损耗,高性能微波和毫米波设备非常重要。高达10,000 ohm.cm的最高电阻率是浮区(FZ)生长的硅,该硅以小批量且中等晶片直径生产。更常见的Czochralski(CZ)Si可以实现约1000 ohm.cm的电阻率,但是晶圆中包含的氧气会导致形成热施主,其施主浓度(〜1015 cm -3)明显高于掺杂剂浓度(〜1012-cm)。 -10 13 cm-3)的高电阻率Si会导致电阻率变化并可能导致高电阻率p型硅的类型转换。在这项研究中,电容电压(CV)表征用于研究p型高电阻绝缘硅(HRSOI)晶圆的施主形成和类型转换,以及使用肖特基接触对HRSOI晶圆进行CV表征所面临的挑战突出显示。块状或绝缘体上硅(SOI)晶片的最大电容由栅极/接触面积决定。在高电阻率的SOI晶片的C-V表征过程中,铝直接与Si膜接触(肖特基接触);观察到最大电容比接触面积大得多,这表明由于薄膜电阻和掩埋氧化物电容的分布传输线而引起的偏压扩散。另外,在累积区域中观察到“ S”形的C-V图。各种因素的影响,例如:频率,接触和衬底尺寸,栅极氧化物,SOI膜厚度,膜和衬底掺杂,载流子寿命,接触功函数,温度,光,退火温度和辐射对HRSOI的CV特性的影响与其他类型的晶片相比,HRSOI晶片具有最佳的防串扰功能,在防止片上系统配置以防止高频数字电路与敏感模拟电路之间耦合方面,HRSOI晶片起着重要作用。讨论了HRSOI中的基板串扰以及影响串扰的各种因素,例如:基板电阻率,器件之间的间距,掩埋氧化物(BOX)厚度,辐射,温度,退火,光和器件类型。还研究了各种方法来最小化基板串扰,并提出了一种新的表征方法。;由于其掺杂浓度非常低,并且CZ晶片中存在氧气,因此HRS晶片在使用常规技术(例如四点)进行电阻率测量时提出了挑战探头和霍尔测量方法。在这项研究中,重点介绍了使用四点探针,霍尔法和CV轮廓进行精确电阻率测量的挑战,并提出了一种基于阻抗谱测量的HRS晶片电阻率提取新方法,该方法使用聚合物电介质(例如聚苯乙烯和聚甲基丙烯酸甲酯(PMMA))进行)。

著录项

  • 作者

    Nayak, Pinakpani.;

  • 作者单位

    Arizona State University.;

  • 授予单位 Arizona State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2012
  • 页码 268 p.
  • 总页数 268
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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