Design of a broadband PLL solution for burst-mode Clock and Data Recovery in all-optical networks.

摘要

All-Optical networks have been proposed as a solution to meet growing demand for broadband access. An essential component in these networks will be new Clock and Data Recovery devices which can recover burst-mode traffic. This a significantly different challenge from conventional, continuous-mode CDR. Burst-mode data originates at various sources and arrives at the receiver with different phases, potentially changing by ±π Rads. Therefore, new CDR designs are required to adapt to large steps in phase upon each new burst to maintain BER integrity. This must be accomplished on the order of ns if All-Optical networks are to be viable. While several such designs have been proposed, a clear solution has yet to emerge. This thesis proposes broadband PLLs as a new solution for burst-mode Clock and Data Recovery. The design of a completed broadband Phase-locked CDR ASIC is presented, from original device modeling to implementation and testing.