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A 1.5V multirate multibit sigma delta modulator for GSM/WCDMA in a 90nm digital CMOS process.

机译:适用于GSM / WCDMA的1.5V多速率多比特sigma delta调制器,采用90nm数字CMOS工艺。

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摘要

The development of low-voltage and low-power mixed signal CMOS integrated circuits has been one of the key objectives in the last decade. Thus, a significant amount of effort has been devoted for this purpose. There are two main reasons that fuel this need. First reason is the increasing demand for portable battery operated systems. The second one is the ongoing transistor scaling. Analog to digital converters based on Sigma Delta modulators are widely used in the analog front ends of various mixed signal integrated circuits. Hence they have to operate from low supply voltages as well as with minimum power dissipation.; This dissertation investigates the use of digital techniques to replace some of the functionalities that were traditionally performed by analog circuits. By doing so, the aim is to increase the share of digital blocks in the Sigma Delta system and decrease area and power consumption of the modulator. This dissertation also investigates the design techniques of low-voltage, power efficient analog building blocks that are used in the design of a Sigma Delta modulator for wireless applications (i.e., GSM and W CDMA).; In order to demonstrate the techniques presented here, a prototype Sigma Delta modulator is designed and fabricated in a 90nm five metal single poly n-well CMOS process. The modulator is realized with fully-differential stray insensitive switched capacitor integrators. Both integrator stages use a fully differential folded cascode operational transconductance amplifier with switched capacitor common mode feedback to set the common mode voltages of the output nodes. A careful capacitor scaling is performed in the second integrator stage in order to take advantage of the noise shaping that is due to the first integrator stage. The presented Sigma Delta modulator achieves 68.6/42.8dB peak Signal-to-Noise and Distortion ratio (SNDR) and dissipates 1.1/1.9mA of current in GSM (200 kHz) and WCDMA (1.94 MHz) modes, respectively.
机译:过去十年来,低电压和低功率混合信号CMOS集成电路的开发一直是主要目标之一。因此,为此目的已经投入了大量的精力。产生这种需求的主要原因有两个。第一个原因是对便携式电池操作系统的需求不断增长。第二个是正在进行的晶体管缩放。基于Sigma Delta调制器的模数转换器广泛用于各种混合信号集成电路的模拟前端。因此,它们必须以低电源电压以及最小的功耗工作。本文研究了数字技术的使用,以取代传统上由模拟电路执行的某些功能。这样做的目的是增加Sigma Delta系统中数字模块的份额,并减少调制器的面积和功耗。本论文还研究了低电压,高能效模拟模块的设计技术,这些技术被用于无线应用(即GSM和W CDMA)的Sigma Delta调制器的设计中。为了演示此处介绍的技术,以90nm五金属单多晶硅n阱CMOS工艺设计和制造了Sigma Delta调制器原型。该调制器由全差分杂散不敏感开关电容积分器实现。两个积分器级均使用带开关电容器共模反馈的全差分折叠共源共栅共变换放大器,以设置输出节点的共模电压。为了在第二积分器级中进行仔细的电容器缩放,以便利用由于第一积分器级引起的噪声整形。提出的Sigma Delta调制器在GSM(200 kHz)和WCDMA(1.94 MHz)模式下分别达到68.6 / 42.8dB峰值信噪比和失真比(SNDR),并耗散1.1 / 1.9mA电流。

著录项

  • 作者

    Altun, Oguz.;

  • 作者单位

    Georgia Institute of Technology.;

  • 授予单位 Georgia Institute of Technology.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2005
  • 页码 116 p.
  • 总页数 116
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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