Design techniques for power efficiency and robustness in scaled high-performance systems.

摘要

Technology scaling leads to smaller transistor feature dimensions, higher circuit integration density, and faster clock frequency. However, these benefits are achieved at the expense of increased power dissipation and power density. High power dissipation and power density raise temperature, degrade system reliability, and increase the cost of heat removal.; In this work, we address the following power-related problems in modern high-performance VLSI systems: (1) The current induced noise, such as IR drop and Ldi/dt noise in power supply network, has become a crucial issue in present-day VLSI circuit design. It may slow down the circuit speed and reduce the noise margin. An integrated architectural/physical design level technique is proposed to optimize the current demand distribution with consideration of floorplan. As a result, the current surge in power supply network and the corresponding current induced noise are minimized. (2) On-chip decoupling capacitor (Decap) has been extensively deployed to minimize the power supply noise. However, leakage power and area overheads incurred by Decap can be significant. A novel Decap design named Gated Decap is proposed to dynamically control leakage power of Decap, with negligible system throughput penalty. (3) Traditionally, a large current spike is generated when a low-power system, such as a microprocessor with dynamic supply scaling, switches back and forth between the active and power saving modes. A novel Carry-Select Adder (CSA) structure, Cascaded CSA (C2SA) is proposed for low power. Such a design does not incur large current spikes when C 2SA switches between different modes. C2SA works with variable latencies (1 or 2 cycles) automatically, thereby enabling more aggressive and robust supply voltage scaling (under the same timing constraint), and thus resulting in significant power saving.