A new delay testing approach based on delay defect detection within slack intervals (DDSI).

摘要

With the rapid development of the VLSI technologies, commonly observed defect mechanisms such as resistive vias, gate oxide contamination, instance opens all lead to increase of the signal delay in circuit paths. For nanometer CMOS designs, the increasing parameter variations as well as the input-dependent nature of the CMOS timing adds more complexity in testing IC delay faults. In this dissertation, a new delay test based on delay defect detection within slack interval (DDSI) is developed to effectively test delay faults for nanometer IC designs. The new method tests the circuit by looking into the output responses within the slack intervals and normalizes the parameter variations by comparing the results against the good neighboring dies. The new method thus has improved fault "observability" compared with the traditional delay tests. Experimental designs were implemented to validate the method and simulation studies were conducted to explore the test efficiency and related yield issues. Delay fault diagnosis based on DDSI was also studied in the dissertation. Practical application of the DDSI in manufacturing test was explored and discussed in the work.