ESDCat: A new CAD software package for full-chip ESD protection circuit design verification.

摘要

Electrostatic Discharge (ESD) induced failure is one of the most devastating reliability problems to ICs (integrated circuits). On-chip ESD protection is therefore required for all IC chips to prevent ESD damages from happening. New CAD (computer-aided design) tools are essential to ESD protection design prediction and verification at full chip level. This work focuses on developing the first intelligent CAD tool package, entitled ESDCat, for full-chip ESD design verification at both layout level and schematic level. At the layout level, the ESDCat package consists of two modules: ESDExtractor, and ESDInspector. ESDExtractor is a new arbitrary ESD protection device extraction CAD tool that allows extraction of all possible ESD protection devices of arbitrary types, intentional or parasitic, from IC layout files. The main function of the ESDInspector is to remove non-critical ESD devices extracted and perform intelligent physical design checking at layout level based upon a novel smart parametric checking mechanism. At the schematic level, ESD device modeling and circuit simulation using HSPICE is discussed. The future work is to develop a mix-mode circuit simulator, called ESDSimulator. Finally, ESDZapper is developed to simulate the complex ESD measurements, called ESD zapping tests.