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Circuit modules for CMOS high-power short pulse generators .

机译:CMOS大功率短脉冲发生器的电路模块。

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摘要

High-power short electrical pulses are important for high-performance functionality integration, such as the development of microelectromechanical/nanoelectromechanical systems (MEMS/NEMS), system on chip (SoC) and lab on chip (LoC). Many of these applications need high-power (low impedance load) short electrical pulses, in addition to CMOS digital intelligence. Therefore, it is of great interest to develop new circuit techniques to generate high-power high-voltage short electrical pulses on-chip.;Results on pulse forming line (PFL) based CMOS pulse generator studies are reported. Through simulations, the effects of PFL length, switch speed and switch resistance on the output pulses are clarified. CMOS pulse generators are modeled and analyzed with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In the 0.13 mum CMOS process with a 500 mum long PFL, post layout simulations show that pulses of 10.4 ps width can be obtained. High-voltage and high-power outputs can be generated with other pulsed power circuits, such as Blumlein PFLs with stacked MOSFET switches. Thus, the PFL circuit significantly extends short and high-power pulse generation capabilities of CMOS technologies. A CMOS circuit with a 4 mm long PFL is implemented in the commercial 0.13 mum technology. Pulses of ~ 160 ps duration and 110-200 mV amplitude on a 50O load are obtained when the power supply is tuned from 1.2 V to 2.0 V. Measurement Instruments limitations are probably the main reasons for the discrepancies among measurement and simulation results.;A four-stage charge pump is presented as high voltage bias of the Blumlein PFLs pulse generator. Since Schottky diode has low forward drop voltage (~ 0.3V), using it as charge transfer cell can have high charge pumping gain and avoid additional control circuit for switch. A four-stage charge pump with Schottky diode as charge transfer cell is implemented in a commercial 0.13 mum technology. Charge pump output and efficiency under different power supply voltages, load currents and clock frequencies are measured and presented. The maximum output voltage is ~ 6 V and the maximum efficiency is ~ 50%.
机译:大功率短电脉冲对于高性能功能集成非常重要,例如微机电/纳米机电系统(MEMS / NEMS),片上系统(SoC)和片上实验室(LoC)的开发。除了CMOS数字智能外,许多这些应用还需要大功率(低阻抗负载)短电脉冲。因此,开发新的电路技术以在芯片上产生大功率高压短电脉冲具有极大的兴趣。;报道了基于脉冲形成线(PFL)的CMOS脉冲发生器研究的结果。通过仿真,明确了PFL长度,开关速度和开关电阻对输出脉冲的影响。使用作为PFL的片上传输线(TL)和作为开关的CMOS晶体管对CMOS脉冲发生器进行建模和分析。在具有500 m长的PFL的0.13 mm CMOS工艺中,布图后仿真显示可以获得10.4 ps宽度的脉冲。高压和大功率输出可以通过其他脉冲功率电路生成,例如带有堆叠式MOSFET开关的Blumlein PFL。因此,PFL电路极大地扩展了CMOS技术的短功率和高功率脉冲生成能力。商业化的0.13微米技术实现了具有4mm长PFL的CMOS电路。当电源从1.2 V调整到2.0 V时,在50O负载下可获得〜160 ps的持续时间和110-200 mV幅度的脉冲。测量仪器的局限性可能是导致测量和仿真结果差异的主要原因。四级电荷泵是Blumlein PFL脉冲发生器的高压偏置。由于肖特基二极管的正向压降很低(〜0.3V),因此将其用作电荷转移单元可以具有较高的电荷泵浦增益,并避免了用于开关的附加控制电路。采用肖特基二极管作为电荷转移电池的四级电荷泵是在商用0.13毫米技术中实现的。测量并给出了不同电源电压,负载电流和时钟频率下的电荷泵输出和效率。最大输出电压为〜6 V,最大效率为〜50%。

著录项

  • 作者

    Geng, Yongtao.;

  • 作者单位

    Clemson University.;

  • 授予单位 Clemson University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2010
  • 页码 62 p.
  • 总页数 62
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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