Through Silicon vias can offer quick time to market of circuits designed in a modular manner and can also be used to customize the product according to the needs of the customers. This gives a way to avoid both excess inventory risks and larger footprints. A through silicon via could be described as, a vertical component through which a backside interconnect for a pair of bonded wafers forming a wafer stack is ultimately cut into a number of stacked dice. Various embodiments have been patented [1, 2] but implementation of these architectures can be inhibited based on thermal, mechanical and electrical requirements. Also as discussed in the previous work [3], on the thermal enhancement of stacked dice using the thermal vias the primary heat flow path for stacking is through the substrate. As the number of stacks increase, the cooling problem is amplified.;Through silicon vias are emerging as a viable technology for transferring heat and in effect creating a thermal short circuit from individual die to the substrate. This was simulated in Ansys workbench, where comparison of maximum junction temperature with and without the use of vias was done.;In the present thesis, extensive thermal analysis is carried out, focusing on the heat transfer enhancement using through silicon vias. However the interconnects are placed at the location of the die pads, instead of placing the vias strictly to optimize thermal management. An existing wire bond die is modified to include through silicon vias and stacked in a 3D form. This is done in order to replace the stacked die wire bond packaging or application specific circuits tailored in the mask level. The CAD models required for this study are developed in Pro/EngineerRTM Wildfire(TM) and thermal simulation is carried out using ANSYSRTM Workbench. Results are discussed in light of applications and economic implication.
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