Challenges in nanometre digital integrated circuit design.

摘要

Technology trends, driven by the desire for higher transistor densities and faster devices, have led to transistor dimensions scaling into the nanometre regime. However, with this continued scaling, digital Integrated Circuits (ICs) have faced many challenges that include: increased leakage power dissipation, increased process variations of transistor parameters and increased sensitivity of ICs to ionizing radiation from terrestrial and cosmic sources. These challenges are having a significant effect on circuit performance and power, making it more difficult to design circuits that achieve a required specification. This thesis presents new techniques for addressing these challenges in digital circuits.; First, a new Static Random Access Memory (SRAM) cell is presented that reduces gate leakage power in caches while maintaining low access latency and stability. The new cell design, compared to a conventional SRAM cell, has one additional transistor and exploits the strong bias towards logic-0 at the bit, level exhibited by the memory value stream of ordinary programs. Then, techniques for reducing leakage power in Field-Programmable-Gate-Array (FPGA) routing switches and look-up tables are presented; the new circuits significantly reduce the leakage power in those circuits with varying amounts of area and/or performance cost.; Next, circuit and architectural techniques that reduce the Soft-Error-Rate (SER) in a Content-Addressable Memory (CAM) are presented; the first technique augments a Ternary-CAM cell with extra transistors to make it more immune to soft errors, and the second technique, applicable to Binary-CAM cells, adds parity bits to each CAM word and then modifies the sensing scheme so that both a match and a one-bit miss constitute a successful search. The main cost of both of these schemes is increased area.; Then a scheme to compensate for Within-Die (WID) variations in domino logic is presented; the new technique reduces the variation in leakage, delay and noise margin with a small area overhead. Finally a new methodology which takes into consideration the effect of WID process variations on a low-voltage parallel system is presented. The new methodology shows that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel system.