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Reconfigurable multithreaded processors for programmable communication systems.

机译:用于可编程通信系统的可重配置多线程处理器。

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Future mobile devices need to support more features than ever before. These devices also need to support emerging communication standards, which have high-throughput requirements for a wide variety of algorithms. To cope with increasing system complexity and shorter design times, there is a shift in the implementation paradigm from hardware platforms that use Digital Signal Processors (DSPs) and custom hardware to fully programmable platforms. Explicitly multithreaded processors provide a platform to exploit the large amounts of thread-level parallelism present in emerging communication applications. Reconfigurable hardware enables devices to adapt to the requirements of new applications. These observations motivate the design of multithreaded DSPs augmented with reconfigurable hardware to meet the high-throughput requirements and to realize the diverse feature sets of emerging communication applications.; This dissertation investigates techniques for adding reconfigurable functional units, called Polymorphic Hardware Accelerators (PHAs), to explicitly multithreaded processors. It proposes architectural support to manage PHAs in a multithreaded, multicore environment. It evaluates throughput improvements due to PHAs for algorithms relevant to the communication domain. This dissertation also presents operations that benefit compute-intensive algorithms in emerging wireless communication systems, and examines their hardware complexity. The proposed technique shows an average speedup of 6.8 on important wireless communication algorithms specified in the Embedded Microprocessor Benchmark Consortium (EEMBC) Telecom Benchmark Suite and Department of Defense's Joint Tactical Radio System Software Communication Architecture (JTRS SCA) Hardware Supplement. It shows an average speedup of 2.6 on compute-intensive, multithreaded algorithms for physical layer processing in the large-scale wireless communication, applications of WiMAX and DVB-T receivers.
机译:未来的移动设备需要支持比以往更多的功能。这些设备还需要支持新兴的通信标准,这些标准对多种算法都具有高吞吐量要求。为了应对不断增加的系统复杂性和更短的设计时间,实现范例已从使用数字信号处理器(DSP)和定制硬件的硬件平台转变为完全可编程的平台。显式的多线程处理器提供了一个平台,可利用新兴通信应用程序中存在的大量线程级并行性。可重新配置的硬件使设备能够适应新应用程序的需求。这些发现促使设计了具有可重配置硬件的多线程DSP,以满足高吞吐量需求并实现新兴通信应用的各种功能。本文研究了为显式多线程处理器添加可重构功能单元(称为多态硬件加速器(PHA))的技术。它提出了架构支持,以在多线程,多核环境中管理PHA。它针对与通信域相关的算法评估由于PHA带来的吞吐量提高。本文还提出了有益于新兴无线通信系统中计算密集型算法的操作,并研究了其硬件复杂性。所提议的技术在嵌入式微处理器基准联盟(EEMBC)电信基准套件和国防部的联合战术无线电系统软件通信体系结构(JTRS SCA)硬件补遗中指定的重要无线通信算法上平均提高了6.8。它显示出在大型无线通信,WiMAX和DVB-T接收器的应用中,用于物理层处理的计算密集型多线程算法的平均速度提高了2.6。

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