Automatic test pattern generator for full scan sequential circuits using limited scan operations.

摘要

In testing sequential circuits with scan chains, the test application time is the main factor that determines the overall cost of testing the circuit. For these circuits, the test application time principally depends on the number flip-flops as well as the number of vectors in the test set. Though test set compaction is one way of reducing test application time, for a significant reduction in testing costs the duration of scan operation has to be reduced. The proposed method achieves this by using limited scan operations where the number of shifts is smaller that the actual length of the scan chain. Thus the compacted test set consists of limited scan operations in places where the scan operation cannot be dropped completely. The method uses an iterative procedure that identifies the vectors that have high fault coverage with minimal shifts in the scan chain.