Jitter analysis of MOS current-mode logic circuits.

摘要

A new analytical model that describes the phenomenon of noise transformation into jitter in non-autonomous current-mode logic (CML) circuits is presented. Jitter generation is modeled as a linear time-varying process, with its time-domain impulse response function, and a frequency-domain system function. The model shows dependence of jitter on a set of circuit parameters, and hence it can be used to predict jitter. In addition, it gives insights into ways to minimize jitter by controlling the circuit parameters. The method is demonstrated on a CML frequency divider with white and flicker device noise, and a CML buffer with deterministic ground noise. Jitter predictions are compared to the results obtained through exhaustive simulation. The new method predicts jitter with an accuracy of up to 1.2%.