Per-pixel floating-point A/D conversion for high-dynamic range, high-frame rate infrared focal plane imaging.

摘要

Infrared focal plane arrays (IR FPAs) have been widely used for medical, scientific, industrial, and military applications. These applications often require a high-frame rate (≥1000 fps) and high-dynamic range (≥19 bits) imaging to capture rapidly changing scenes at very high contrast. However, state-of-the-art FPAs with CMOS readout electronics and external high-speed A/D converters (ADCs) cannot meet these requirements because of the limited throughput of the analog readout and saturation of the integration capacitor that converts the IR detector current to a voltage signal. Several approaches to integrating ADCs with FPAs have been proposed to increase the throughput of the data conversion, and various dynamic range enhancement schemes have been developed to avoid integration capacitor saturation. However, limited power and area budgets for the IR FPAs have precluded the simultaneous use of these techniques.; By using three-dimensional integrated circuit (3-D IC) technology, IR FPAs can be integrated not only with conventional CMOS readout electronics, but also with ADCs and dynamic range enhancement schemes, to achieve both a high frame rate and a high dynamic range. In addition, the simultaneous optimization of the readout electronics, dynamic range enhancement, and ADC provides an opportunity to develop a new architecture that minimizes both power and area.; This dissertation introduces a per-pixel floating-point, dual-slope ADC architecture that achieves a high-frame rate and high-dynamic range IR FPA. Floating-point A/D conversion appears to be an alternate solution for uniform A/D conversion for low-power high-dynamic range data conversion. The proposed per-pixel ADC architecture achieves a high frame rate by removing the analog readout bottleneck between the IR detectors and external ADCs. Moreover, by adjusting the integration time of each pixel based on the detector current strength, the architecture attains a high dynamic range without much increase in power consumption. To improve the uniformity of the per-pixel ADC array, each ADC performs a unique analog offset cancellation combined with a digital correction.; Two experimental prototype arrays have been integrated. A prototype 16 x 16 ADC array integrated in a 0.18-mum CMOS technology achieves a 19-bit dynamic range and 8-bit mantissa resolution at 3000 fps, with a power consumption of only 7 muW/pixel. A second 16 x 16 ADC array integrated in a 3-D 0.18-mum FDSOI technology attains a similar performance; furthermore, each ADC partitioned into three layers successfully fits within a detector size of 50 x 50 mum 2, demonstrating A/D conversion using 3-D IC technology.