Methodes d'acceleration de la simulation analogique utilisee dans des applications necessitant des simulations multiples.

摘要

Although SPICE-like simulators are essential tools for the design of analog circuits, they are not intended to simulate repeatedly the same circuit with slight modifications. Three major applications require such multiple simulations: analog fault simulation, automatic circuit sizing and Monte Carlo analysis. These operations are CPU time intensive. The objective of this research project is the development of techniques allowing the reduction of the CPU time required for multiple simulations by favoring the information sharing between circuits and allowing a tradeoff between CPU time and simulation results accuracy.; The Newton-Raphson algorithm, on which is based the simulation of analog circuits, is very sensitive to the initial solution approximation used and converges to the exact solution after a certain number of iterations. The first computation time reduction approach proposed is the development of methods to end the iterations before convergence of Newton-Raphson algorithm in DC simulation. A tradeoff is then achieved between the CPU time and the accuracy of the simulation results. The two proposed methods require an accurate initial solution approximation and are based on the worst relative variation metric also proposed in this thesis. The first method is to increase the relative tolerance of the SPICE simulator to the required simulation accuracy. The simulation is ended once this accuracy is reached with a low risk of erroneous results and the number of performed iterations is reduced by 20 to 40%. The second method addresses the applications which need comparisons between circuits, among others analog fault simulation. The DC simulation of a considered faulty circuit is ended once its output voltage is accurate enough to immediately classify the fault as detected or not detected. The number of iterations is reduced by a factor of 3, with a low percentage of misclassified faults. The second approach explored in this thesis is to optimize an existing SPICE simulator to rapidly perform multiple simulations of a circuit with slight modifications. The resulting MultiSPICE simulator decreases the computation time required by multiple simulations by taking advantage of (1) a socket connection with the calling application, (2) efficient injection of modifications in nominal circuit, (3) the use of accurate initial DC solution approximations and (4) the use of methods to end DC simulation before convergence. Analog fault simulation, automatic circuit sizing and Monte Carlo analysis applications have been developed to evaluate the performances achieved by MultiSPICE. In DC simulation, the proposed simulator is 85 times faster than the reference simulator for identical simulation results. When methods to end iterations before convergence are used, the computation time gain reaches 125 for a very low risk of erroneous results.