A MEMORY-EFFICIENT PARAMETERIZABLE FPGA IMPLEMENTATION OF THE CDMA2000 TURBO CODEC

摘要

Originally used in deep space telemetry, Turbo codes can now be found in standards for 3G mobile and digital television. This paper describes a highly parameterizable codec design, based around the cdma2000 codec. The codec can be optimally configured for different memory and latency requirements. This is achieved by selecting different parameters depending on the requirements of the user. Results presented show how changing different parameters affects performance. The Turbo codec was tested using the Nallatech Bit Error Rate Test (BERT) platform. The BERT allows any compatible forward error correction system to be tested on a Nallatech hardware emulation system. Using the BERT, parameters such as the channel noise variance can be varied. Results are presented that show how channel noise variance affects performance and a single noise variance value that can be used with multiple code rates is obtained from these results.