Wideband channelized receiver possibilities with 0.18-um CMOS technology

摘要

Abstract: Channelized receivers are useful in communications systems that use frequency division multiplexing, and in wideband radar and electronic warfare receivers. In present wideband communications equipment, the channelization function is done typically with discrete elements such as mixers and surface acoustic wave (SAW) bandpass filters on a single channel basis. Recently much activity has been directed to using digital techniques and devices to make smaller, cheaper receivers. Following this trend, this paper exploits the 'Timeline' 0.18 micron CMOS technology recently announced by Texas Instruments and show the bandwidths, levels of system integration, and package sizes that become possible with the Timeline technology. The design example shown is a digital channelizer for a system with 150 MHz total bandwidth including 60 channels on 2.5 MHz channel centers. A polyphase filter bank algorithm with 6x oversampling compared to the channel spacing is used. The design is suitable for a burst communication receiver. With the Timeline technology, an ASIC that implements two maximally decimated filter banks at the above bandwidths is shown. The ASIC fits onto a 20 mm by 20 mm die and consumes about 7 watts. Three such ASICs are then needed to implement the complete 6x oversampled filter bank, which will output 60 complex channels at 15 MSPS for about 20 watts. !0