Dynamic Power Management of Network-on-Chip

摘要

Systems on Chip performances in terms of speed and power dissipation is becoming dominated by communication between the cores. To overcome the limitations of traditional bus architectures, nowadays Network-on-Chip architectures are adopted. The Dynamic Power Management architecture and algorithm and Network-on-Chip topology and routing algorithms should be selected considering that they both effect in a complex and complementary way the network throughput and power dissipation. This paper presents the analysis of the effect of Dynamic Power Management strategies on Network-on-Chip performances.