Conventional and slurry free CMP of polymer layers for Gbit DRAM

摘要

A new planarization method for photo resist layers used for etch back is presented. The influence of slurry composition on polishing results (speed, selectivity) was investigated. Process control, Integration aspects as well as Cost of Ownership are discussed. Precise and highly uniform height control of layer thickness and recess depths, both on the wafer scale and within Chip becomes a very important issue for state of the art DRAM manufacturing process technologies. Deep Trench Capacitor based technologies with or without vertical transistors are a very powerful way to scale down the required space for an individual memory cell for DRAM and embedded DRAM Technologies.