Modeling the Impact of Packaging Stress on Device Performance

摘要

In this study the stress evolution for the entire transistor fabrication process is simulated and the packaging stress is modeled as the external pressureormal stress acting on the boundaries of the transistor unit cell. The impact on device performance from both the fabrication stress and the packaging stress is investigated using a classical piezo-resistance mobility model. The effect of the packaging stress on device mobility can be either beneficial or detrimental depending on whether the stress is tensile or compressive, on stress pattern, its magnitude, and the transistor type. The results suggest that utilizing both the fabrication stress and the packaging stress for stress engineering can lead to additional device performance enhancements.