首页> 外文会议>Symposium Proceedings vol.863; Symposium on Materials, Technology and Reliability of Advanced Interconnects; 20050328-0401; San Francisco,CA(US) >Effect of Microstructure and Dielectric Materials on Stress-Induced Damages in Damascene Cu/Low-k Interconnects
【24h】

Effect of Microstructure and Dielectric Materials on Stress-Induced Damages in Damascene Cu/Low-k Interconnects

机译:微观结构和介电材料对镶嵌铜/低k互连中应力引起的损伤的影响

获取原文
获取原文并翻译 | 示例

摘要

The line width dependence of stress in damascene Cu was examined experimentally as well as with a numerical simulation. The measured hydrostatic stress was found to increase with increasing line width. The larger stress in an interconnect with large dimension is attributed to the larger grain size, which induce higher growth stress in addition to thermomechanical stress. A stress model based on microstructure was constructed and the contribution of the growth and thermal stress of the damascene lines were quantified using finite element analysis. It was found that the stress of the via is lower than that of wide lines when both the growth stress and thermal stress were considered. This stress gradient between via and line, which is the driving force of vacancy diffusion, is larger when the low-k with lower stiffness and higher thermal expansion is used for dielectric layer. For this reason, the Cu/low-k can be more vulnerable to stress-induced voiding.
机译:通过实验以及数值模拟研究了镶嵌铜中应力的线宽依赖性。发现测得的静水压力随着线宽的增加而增加。具有较大尺寸的互连中较大的应力归因于较大的晶粒尺寸,除了热机械应力外,晶粒还导致较高的生长应力。建立了基于微观结构的应力模型,并通过有限元分析定量了镶嵌线的生长和热应力的贡献。当同时考虑生长应力和热应力时,发现通孔的应力低于宽线的应力。当将具有较低刚度和较高热膨胀的低介电常数用于介电层时,通孔和线之间的应力梯度(即空位扩散的驱动力)会更大。因此,Cu / low-k可能更容易受到应力引起的空隙的影响。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号