Session 2 overview: High-bandwidth DRAM PRAM: Memory subcommittee

摘要

VLSI applications today require high-volume power-efficient DRAM. Achieving high bandwidth at low voltages remains a significant challenge for DRAM design. In ISSCC 2012, a new DDR4 4Gb DRAM demonstrates a data rate up to 3.2Gb/s/pin for server applications. A new LPDDR3 4Gb DRAM for mobile applications has a data rate up to 1.6Gb/s/pin. DRAM technology has advanced to 23nm and 4Gb density is becoming mainstream. For the emerging memory technology of PRAM (phase-change RAM), an 8Gb chip is realized with the minimum feature-size of 20nm. Significant progress is also made in the TSV (through-silicon via) technology along with new I/O circuit design for more power-efficient memory interfaces. The papers in this session present the latest technologies and high-bandwidth circuit techniques to improve the performance and density of both DRAM and PRAM.