A 40nm CMOS all-digital fractional-N synthesizer without requiring calibration

摘要

Bang-Bang all-digital PLLs [1] for applications such as digital clock multiplication have existed for a long time, but show limited phase noise performance. Pioneering recent work [2-5] has demonstrated frequency synthesizers that meet the performance requirements of wireless communications systems, while containing no analog circuits except for an LC-oscillator. In order to build an All-Digital Phase-Locked Loop (ADPLL), it is necessary to measure the oscillator''s momentary phase accurately, in a digital way, since the output phase noise at frequencies within the PLL loop bandwidth is ultimately limited by the time quantisation step Δt of this phase measurement [6]: L=20.log₁₀ (Δt·ω_osc/√12·√f_sample) [dBc/Hz] (1) In [2-5], a Time-to-Digital Converter (TDC) is used to measure the oscillator''s phase with a resolution of a single inverter delay. However, this approach requires calibration of the TDC conversion gain. Previous work [2] included a small microprocessor incorporated in the PLL circuit, to perform all necessary calculations related to the calibration. Obviously, this renders the circuit complex, is prone to calibration errors and consumes power and area. In this paper, an alternative approach is presented, allowing all-digital frequency synthesizers that meet the requirements for wireless communications standards, that benefit from the benign scaling properties, porting properties, process independence and controlled design flow, inherent to digital circuits, but that, on the other hand, do not require the burden of calibration and associated calculations.