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Ferroelectric Thickness Dependent Domain Interactions in FEFETs for Memory and Logic: A Phase-field Model based Analysis

机译:用于存储器和逻辑的FEFET中的铁电厚度依赖性域相互作用:基于基于相位场模型的分析

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We present a phase-field simulation framework for ferroelectric (FE)-FET which captures multi-domain effects by self-consistently solving 2D time-dependent Ginzburg-Landau (TDGL), Poisson's, and semiconductor charge/transport equations. Using our phase-field model and experiments, we analyze electrostatics-driven multi-domain formation and voltage-induced polarization (P) switching for different FE thickness (TFE). We show that for TFE = 5nm - 10 nm, FEFETs exhibit multi-level memory functionality; while for TFE = 1.5nm - 3 nm, FEFETs can serve as non-hysteretic switches with enhanced gate control. Our results signify that as TFE is reduced from 10nm to 5nm, denser domain patterns emerge in FE, and the dominant P-switching mechanism changes from nucleation to domain-wall motion based leading to a decreased memory window with TFE scaling. Moreover, as TFE is scaled further from 3nm to 1.5nm, effective permittivity of the gate stack increases due to multi-domain electrostatic interactions.
机译:我们为铁电(Fe)的阶段仿真框架提供了一种通过自我辅助的2D时间依赖的Ginzburg-Landau(TDGL),泊松和半导体电荷/传输方程来捕获多域效应。使用我们的阶段模型和实验,我们分析静电驱动的多域形成和电压诱导的极化(P)切换,用于不同的Fe厚度(T fe )。我们表明了这一点 fe = 5nm - 10 nm,FEFET表现出多级内存功能;而对于t. fe = 1.5nm - 3 nm,FFFET可用作具有增强型栅极控制的非滞后开关。我们的结果表示,如图1所示 fe 从10nm到5nm的减少,更密度域模式在FE中出现,主导的P切换机制从成核变为基于域 - 基于域 - 壁运动,导致与T的减少的内存窗口。 fe 缩放。而且,如t fe 进一步从3nm到1.5nm缩放,由于多域静电相互作用,栅极堆叠的有效介电常数增加。

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